Beyond RTL: Advanced Digital System Design

This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex IP blocks and high-speed buses and interconnection networks. This tutorial addresses the following emerging challenges: architectural exploration, HW/SW co-design, complex control and concurrency, correctness and verification, timing closure, and low-power. The tutorial will focus on language facilities and synthesis techniques that dramatically simplify and shorten the process of correct chip design by raising the level of abstraction on multiple dimensions without sacrificing final hardware quality. The tutorial will cover the following topics in detail: High-Level Language Facilities: Modeling concurrency and managing shared resources with atomic rules Building scalable designs with modules and rule-based interfaces Synthesizing rules into hardware, including scheduling Improving correctness through advanced types and type-checking Managing power with systematic clock domains Leveraging advanced parameterization to promote reuse Methodologies: Systematic refinement from transaction-level models to synthesizable implementations Architectural exploration for optimal designs Simulation and co-simulation of complex systems How verification is shortened by designing with abstraction Systematic debugging/verification: functional correctness vs. performance correctness Systematic modification for timing closure: retiming and rebalancing Lectures will include numerous code examples and walk-throughs